High Speed Low Power Network Processors: Efficient Power Management Techniques
نویسنده
چکیده
Power consumption is the bottleneck in achieving high performance. Power dissipation needs to be looked into the various levels of the design namely: circuit level, device level, architecture level and system level. With the increase in the networking, network processors (NP) have emerged as platform providing high performance and flexible in building the routers. Its observed from the survey of previous work, the processing elements, the micro engines (ME) of the NP consumes the power more. The simulation tool for this analysis used is the NepSim. Hence, the effort is to be made in reducing the power of the MEs. This paper initially briefs on the basics of power consumption in VLSI systems and the architecture of NP IXP1200. The emphasis is done on the analysis of power dissipated/consumed at the different levels of NP namely: packet level, instruction level and the architecture level. The later part of the paper wholly concentrates on the power management techniques at the architectural level. These different techniques are: clock gating, dynamic voltage and frequency scaling, power gating and very new method of designing the architecture in an
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